Silicon-on-insulator (SOI) semiconductor devices, such as silicon-on-sapphire (SOS) transistors, are increasingly being used in very large scale integration (VLSI) circuits. However, the high defect structure of the silicon layer has been regarded as a limiting factor in exploiting the full potential of silicon-on-sapphire semiconductor devices. These defects are particularly troublesome when the silicon thickness is scaled down from 0.5 micron to 0.3 micron and less to meet the requirements of advanced VLSI circuits.
The crystallographic defects in the silicon are caused by a reaction between the sapphire substrate and the silicon film. Lattice mismatch and differences in the thermal- expansion coefficients of the silicon layer and the sapphire substrate also contribute to the formation of the crystallographic defects. Devices formed in thin silicon layers have low carrier mobility, slow operating speeds and low drain currents.
There is a continuing effort to reduce the number of crystallographic defects in the silicon layer. The silicon properties have been improved by modifying the substrate surface finish and controlling the silicon growth process. These techniques have significantly improved the silicon properties; however, it has become necessary to turn to post-deposition processes to improve the crystalline quality in order to meet the requirements associated with advanced VLSI circuits.
Solid phase epitaxy (SPE) is an example of a post-deposition process used to enhance the crystallographic and semiconducting properties of the silicon layer. In the conventional SPE process, silicon ions are implanted into the monocrystalline silicon layer to form a subsurface amorphous region extending down to the sapphire substrate. However, a small region of the original crystalline material remains at the surface of the silicon layer. The structure is then annealed at a temperature greater than about 550.degree. C. The region of crystalline material at the surface of the silicon layer acts as a nucleation seed for the recrystallization of the amorphous region. This recrystallized region of the ; silicon layer is substantially free of crystallographic defects.
Since the SPE process increases the crystallographic perfection of the silicon layer where the channel region is formed, the carrier mobility, the operating speeds and the drain currents of the devices are increased. However, this increased device performance is only realized when the device is not exposed to radiation. When the device is exposed to radiation, the performance is severely degraded because of high back-channel leakage currents. While this effect may be partially offset by an initial substrate annealing procedure and by doping the back-channel with the appropriate dopant, a technique is needed to produce a silicon-on-insulator composite with a higher degree of radiation hardness.